Advance nanoscale patterning technology requires high resolution lithography, from ultraviolet (UV, i-line system) to deep ultraviolet (DUV, KrF system) until extreme ultraviolet (EUV), but the compatibility study of new resist types and wet etchant is lacking. The compatibility is defined as the duration of a photoresist being able to withstand in wet oxide etchant. Poor compatibility has potential resist lifting and/or penetration during wet etch process, which causes electronic device performance drifting. Currently, wet oxide etching is widely used in the gate oxide wet etch using patterned resist, as well as in the backside oxide removal with blanket resist front-side coverage. In this paper, we explore the compatibility and understand the impact factors, based on commonly used resist (i.e., KrF and i-line system resist) and wet etch chemicals (i.e. HF based etchant) in industry. It is important to do a quick and straightforward compatibility check before we implement new resists on actual product wafers, to prevent poor compatibility caused resist lifting and/or penetration during wet etch process. Based on oxide thickness check and resist lifting phenomena, it is found that resist baking condition, resist polymer type, resist composition, and lag time from resist coating to wet oxide etching all will affect the compatibility between HF based etchant and resist.

Single-port ferroelectric FET (FeFET) that performs write and read operations on the same electrical gate prevents its wide application in tunable analog electronics and suffers from read disturb, especially in the high-threshold voltage (VTH) state as the retention energy barrier is reduced by the applied read bias. To address both issues, we propose to adopt a read disturb-free dual-port FeFET where the write is performed on the gate featuring a ferroelectric layer and the read is done on a separate gate featuring a nonferroelectric dielectric. Combining the unique structure and the separate read gate, read disturb is eliminated as the applied field is aligned with polarization in the high-VTH state, thus improving its stability, while it is screened by the channel inversion charge and exerts no negative impact on the low-VTH state stability. Comprehensive theoretical and experimental validation has been performed on fully depleted silicon-on-insulator (FDSOI) FeFETs integrated on a 22 nm platform, which intrinsically has dual ports with its buried oxide layer acting as the nonferroelectric dielectric. Novel applications that can exploit the proposed dual-port FeFET are proposed and experimentally demonstrated for the first time, including FPGA that harnesses its read disturb-free feature and tunable analog electronics (e.g., frequency tunable ring oscillator in this work) leveraging the separated write and read paths.

Abstract Physical Failure Analysis (PFA) is essential for SRAM yield learning, especially in new technologies or FAB transfers. For this to be successful, physical coordinates for tested bitcell failures must be accurately calculated and verified. The timeline for this process can vary dramatically based on the extent and complexity of any issues. This paper details the successful use of fault localization on isolated, voltage sensitive failures to achieve confidence in verification of physical location prior to PFA.

Abstract The first step in die-level failure analysis is to narrow the search to a specific circuit or transistor group. Then begins the post-isolation process which entails further localizing the defect, determining its electrical, physical, and chemical properties, and examining its microstructure in order to identify the root cause of failure. This chapter assesses the tools and techniques used for those purposes and the challenges brought on by continued transistor scaling, advanced 3D packages, and new IC architectures. The areas covered include sample preparation, nanoprobing, microscopy, FIB circuit edit, and scanning probe microscopy.

Abstract The first step in die-level failure analysis is to narrow the search to a specific circuit or transistor group. Then begins the post-isolation process which entails further localizing the defect, determining its electrical, physical, and chemical properties, and examining its microstructure in order to identify the root cause of failure. This chapter assesses the tools and techniques used for those purposes and the challenges brought on by continued transistor scaling, advanced 3D packages, and new IC architectures. The areas covered include sample preparation, nanoprobing, microscopy, FIB circuit edit, and scanning probe microscopy.